Method for operating a memory device

ABSTRACT

A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation-in-part application of U.S.Ser. No. 10/211,248, filed Aug. 5, 2002 now U.S. Pat. No. 6,700,818,which claims priority from U.S. provisional application Ser. No.60/352,549, filed Jan. 31, 2002, both applications are herebyincorporated by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates generally to operating memory cells ofnon-volatile memory (NVM) arrays, such as programming and erasing, andparticularly to methods for reducing pulse operations of such arrays.

BACKGROUND OF THE INVENTION

Memory cells are used in the implementation of many types of electronicdevices and integrated circuits, such as, but not limited to, erasable,programmable read only memories (EPROMs), electrically erasable,programmable read only memories (EEPROMs), and flash EEPROM memories.Memory cells are used to store the data and other information for theseand other integrated circuits.

Non-volatile memory (NVM) cells generally comprise transistors withprogrammable threshold voltages. For example, a floating gate transistoror a split gate transistor has a threshold voltage (Vt) that isprogrammed or erased by charging or discharging a floating gate locatedbetween a control gate and a channel in the transistor. Data is writtenin such memory cells by charging or discharging the floating gates ofthe memory cells to achieve threshold voltages corresponding to thedata.

The act of programming the cell involves charging the floating gate withelectrons, which increases the threshold voltage Vt. The act of erasingthe cell involves removing electrons from the floating gate, whichdecreases the threshold voltage Vt.

One type of non-volatile cell is a nitride, read only memory (NROM)cell, described in U.S. Pat. No. 6,011,725, the disclosure of which isincorporated herein by reference. Programming and erasing of NROM cellsare also described in U.S. Pat. No. 6,011,725.

Unlike a floating gate cell, the NROM cell has two separated andseparately chargeable areas Each chargeable area defines one bit. Theseparately chargeable areas are found within a nitride layer formed inan oxide-nitride-oxide (ONO) stack underneath the gate. When programminga bit, channel hot electrons are injected into the nitride layer. Thisis generally accomplished by the application of a positive gate voltageand positive drain voltage, the magnitude and duration of which aredetermined by different factors related to the amount of programmingrequired.

NROM cells may be single bit. Alternatively, they may have more than onebit, wherein two individual bits, a left-side bit and a right-side bit,are stored in physically different areas of the nitride layer. Each bitmay be single level or multi-level (“MLC”), i.e., may be programmed todifferent voltage levels.

One procedure for programming bits in NROM cells with programming pulsesis described in Applicant's copending U.S. patent application Ser. No.09/730,586, entitled “Programming And Erasing Methods For An NROMArray”, the disclosure of which is incorporated herein by reference.

The application of pulses to operate (program or erase) the NROM arraymay pose a problem for mass storage or code flash applications. Forexample, in programming a mass storage array, a major requirement is afast programming rate, in the range of at least 2 MB/sec. The channelhot electron injection (CHE) used for programming may require arelatively high programming current, e.g., approximately 100 μA percell. In addition, each programming step may comprise switching andsubsequent verification steps. These factors may limit the amount ofcells that may be programmed in parallel, to about 64 cells, forexample.

Other complications that may hinder achieving fast, parallel programmingrates include, among others, temperature dependence, cell lengthdependence (e.g., die to die and within a die), neighboring cell statedependence, second bit state dependence, and others. For example, FIG. 1illustrates an effect of cell length on programming NROM cells. FIG. 1illustrates the change in threshold voltage as a function of drainvoltage used to program the cell. In the illustrated example, a firstgraph, denoted by the reference numeral 77, shows the change inthreshold voltage as a function of drain voltage for a cell with alength of 0.5 microns. A second graph, denoted by the reference numeral78, shows the change in threshold voltage as a function of drain voltage(Vd) for a cell with a length of 0.55 microns. It is seen that theslightly longer cell requires a higher drain voltage to achieve the samechange in threshold voltage as the shorter cell.

As another example, FIG. 2 illustrates an effect of temperature onprogramming NROM cells. FIG. 2 illustrates the change in thresholdvoltage as a function of drain voltage (Vd) used to program the cell. Inthe illustrated example, a first graph, denoted by the reference numeral79, shows the change in threshold voltage as a function of drain voltagein an ambient of 20° C. A second graph, denoted by the reference numeral80, shows the change in threshold voltage as a function of drain voltagein an ambient of 85° C. It is seen that the warmer ambient requires ahigher drain voltage to achieve the same change in threshold voltage asthe cooler ambient.

Determination of programming pulses is also complicated by the fact thatthe cell parameters and operating conditions are usually initiallyunknown. Utilizing large programming pulse steps may reduce the totalamount of programming pulses required to program the array. However,this may be disadvantageous because it may result in a wide and varieddistribution of threshold voltages in the programmed cells of the array,which may reduce product reliability.

Alternatively, accurate verification of the cell threshold voltage andcomparison of the threshold voltage to a variety of references mayreduce the amount of programming pulses and provide faster convergenceto the desired programmed threshold voltage level. However, such amethod may incur a substantial overhead in the form of multiple verifypulses (e.g., one per reference), which is an undesirable time penalty,or may require an intricate parallel reference design, which is anundesirable chip area penalty.

SUMMARY OF THE INVENTION

The present invention seeks to provide methods for operating(programming or erasing) bits of memory cells in memory arrays, and forreducing pulse operations of such arrays. The invention is described indetail hereinbelow with reference to memory cells of NVM arrays, andparticularly to multi-level NROM cells, wherein programming and erasinggenerally involve changing the threshold voltage level of a bit to atarget threshold level. However, it should be emphasized that theinvention is not limited to NVM arrays, nor to changing the thresholdvoltage levels of bits. Rather, the present invention is applicable forany non-volatile or volatile memory array whose operation is based onchanging any kind of electrical, physical and/or mechanical propertiesof the cell array. The invention may be implemented in a variety ofapplications, such as but not limited to, mass storage or code flashapplications, for example.

In accordance with an embodiment of the present invention, a set ofcells in the array may be operated to determine their behaviorcharacteristics upon the application of pulses to program or erase.After analyzing how the threshold voltage changes in accordance with thepulses, the rest of the array or some portion thereof may be programmed(or erased) en masse with a significantly reduced number of pulses andverifies. In some cases, the rest of the array may be programmed (orerased) with just one pulse. The additional operation pulses may belearnt and added to previous analysis and may determine the nextoperating pulse if more than one pulse is applied.

There is thus provided in accordance with an embodiment of the inventiona method of operating a set of memory cells in a memory array, themethod including applying a first operating pulse to a terminal of afirst cell, the first operating pulse is intended to place the firstcell into a predefined state, and applying a second operating pulse to aterminal of a second cell, the second operating pulse is intended toplace the second cell to the predefined state, and the pulsecharacteristics of the second operating pulse are a function of theresponse of the first cell to the first operating pulse.

Further in accordance with an embodiment of the invention the methodincludes a step of applying a third operating pulse to a terminal of athird cell, the third operating pulse is intended to place the thirdcell to said predefined state, and the pulse characteristics of thethird pulse are a function of the response of the first and the secondcells to the first and the second operating pulses, respectively.

Further in accordance with an embodiment of the invention the methodadjusts the pulse characteristics of the second operating pulse byadjusting the duration of the second operation pulse.

Still further in accordance with an embodiment of the invention themethod adjusts the pulse characteristics of the second operation pulseby adjusting the amplitude of the second operation pulse.

In accordance with another embodiment of the invention a control circuitfor operating a set of memory cells in a memory array is provided. Thecontrol circuit includes a charge circuit adapted to produce a firstoperating pulse to a terminal of a first cell intended to place thefirst cell into a predefined state, and a logic unit adapted todetermine pulse characteristics of a second operating pulse as afunction of the response of the first cell to the first operating pulse.

Further in accordance with an embodiment of the present invention thelogic unit is adapted to determine pulse characteristics of a thirdoperating pulse as a function of the response of the first cell and thesecond cell to the first and second operating pulses, respectively

Further in accordance with an embodiment of the present invention thelogic unit is adapted to adjust the duration of the second operationpulse.

Further in accordance with an embodiment of the present invention thelogic unit is adapted to adjust the amplitude of said second operationpulse.

In accordance with an embodiment of the present invention the controlcircuit further includes a memory buffer adapted to store data receivedfrom the set of memory cells.

In accordance with another embodiment of the invention a system foroperating a set of memory cells in a memory array is provided. Thesystem includes a memory array, a sense amplifier adapted to determine aresponse of operated cells, and a control circuit adapted to produce afirst operating pulse to a terminal of a first cell intended to placethe first cell into a predefined state. The control circuit is furtheradapted to determine pulse characteristics of a second operating pulseas a function of the response of the first cell to the first operatingpulse.

Further in accordance with an embodiment of the invention the controlcircuit is adapted to determine pulse characteristics of a thirdoperating pulse as a function of the response of the first cell and thesecond cell to the first and second operating pulses, respectively.

Further in accordance with an embodiment of the invention the controlcircuit is adapted to adjust the duration of said the operation pulse.

Further in accordance with an embodiment of the invention the controlcircuit is adapted to adjust the amplitude of said second operationpulse.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with theappended drawings in which:

FIG. 1 is a simplified graph of an effect of cell length on programmingspeed for two different cell lengths;

FIG. 2 is a simplified graph of an effect of temperature on programmingspeed for two different ambient temperatures;

FIG. 3 is a flow chart of a method for operating (e.g., programming orerasing) bits of memory cells in a non-volatile memory cell array, inaccordance with a preferred embodiment of the present invention; and

FIG. 4 is a simplified graph comparing the distribution of the thresholdvoltages of the cells of the entire array, respectively after theapplication of a single programming pulse, after a plurality of steppedprogramming pulses, and after a single programming pulse plus anadditional supplementary programming pulse in accordance with apreferred embodiment of the present invention.

FIG. 5 is a block diagram of a control circuit, a memory array and asense amplifier, in accordance with an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Reference is now made to FIG. 3, which illustrates a method foroperating bits of memory cells in a memory cell array, in accordancewith an embodiment of the present invention. FIG. 3 is shown anddescribed herein for programming the bits, but it is appreciated thatthe invention is not limited to the operation of programming, and theinvention may be applied to other operations, such as but not limitedto, erasing.

A set of memory cells or bits of the array may be selected (step 101).The set size may be any arbitrary size, such as but not limited to, 64cells, for example. The bits in the set may then be programmed (step102), such as by using a stepped programming algorithm. A suitablestepped programming algorithm is the one described in the Applicant'sabovementioned copending U.S. patent application Ser. No. 09/730,586,entitled “Programming And Erasing Methods For An NROM Array”. The methodcomprises applying progressive pulses or steps of programming voltagesthat progressively raise the threshold voltages of the bits to thedesired programmed level. The number of programming pulses or steps maycomprise any number, such as but not limited to, 8 steps, and maycomprise different gate and drain voltages (source may be grounded),respectively applied to word lines and bit lines of the array. Thevoltages may be applied for different durations of time as well duringthe stepped algorithm. Another example for a programming algorithm is aprogramming algorithm for an MLC array. This programming algorithm isdescribed in the Applicant's copending U.S. patent application Ser. No.10/155,217, entitled “A Method Of Programming Nonvolatile Memory Cells”.The method for programming an MLC having more than one programmed stateto a target programmed state comprises applying a drain, a source and agate voltage to the MLC, and verifying a threshold voltage level of theMLC. If the verified threshold voltage level of the MLC is below thethreshold voltage level associated with the target programmed state, thedrain voltage may be increased and the gate voltage may be maintained ata constant level during at least a part of the step of increasing. Thesteps of applying, verifying, increasing and maintaining may be repeateduntil the MLC's threshold voltage level is substantially equal to thethreshold voltage level associated with the target programmed state. Thenumber of said steps may also comprise any number. The application ofthe stepped programming algorithm or of the programming algorithm forthe MLC array on the set of bits is referred to as the learning phase,wherein the response nature of the bits to the programming voltages maybe learned and perhaps stored in memory. Preferably, the overall timeallocated to the learning phase is negligible compared to the totalarray programming time, such as due to a small size of the set.

The response of the bits to the programming operation may then beanalyzed, such as by a processor or a logic unit (step 103). Theanalysis may include information about the operation pulse including butnot limited to, pulse height and length, resultant distribution tail,and amount of pulses, for example. The analysis may determine the oneoperating pulse that singly changes electrical, physical and/ormechanical properties of the bits a predefined amount (step 104). Forexample, in the programming operation, the processor may determine theprogramming pulse that singly increases the threshold voltages of thebits a predefined amount (step 105). In an erasing operation, theprocessor may determine an erasing pulse that singly lowers thethreshold voltages of the bits a predefined amount (step 106).

Threshold voltage of non-volatile memory cells is just one example ofelectrical, physical and/or mechanical properties that may be analyzedin the learning phase. Another examples include piezoelectric andmagnetoresistive properties of ferroelectric or ferromagnetic materials.For example, magnetic memory devices, such as magnetic random accessmemory devices, may include ferromagnetic layers separated by anon-magnetic layer. Information is stored as directions of magnetizationvectors in magnetic layers. Magnetic vectors in one magnetic layer, forexample, may be magnetically fixed or pinned, while the magnetizationdirection of the other magnetic layer may be free to switch between thesame and opposite directions as information, referred to as “parallel”and “anti-parallel” states, respectively. In response to parallel andanti-parallel states, the magnetic memory device represents twodifferent resistances. The resistance indicates minimum and maximumvalues when the magnetization vectors of two magnetic layers point insubstantially the same and opposite directions, respectively.Accordingly, the change in the direction of the magnetization vectors orthe change in the resistance are other examples of electrical, physicaland/or mechanical properties that may be analyzed in the learning phaseof the present invention.

The operating pulse, which has been determined as a function of theresponse of the electrical, physical and/or mechanical property (e.g.,threshold voltage) of the bits, preferably incorporates the influence ofeffects or phenomena, such as but not limited to, ambient temperature,cell critical dimensions, array architecture, and others.

The rest of the array (or some portion thereof) may then be operated on(e.g., programmed or erased) with at least one further operating pulsewhose voltage values are that of the operating pulse that has beendetermined in step 104 as a function of the response of the thresholdvoltages of the bits (step 107). Alternatively, the rest of the array(or some portion thereof) may then be operated on (e.g., programmed orerased) with at least one further operating pulse whose voltage valuesare that of the operating pulse that has been determined in step 104,modified by a tolerance (step 108). Utilization of this operating pulse(optionally, with or without some delta) as the starting point foroperating (e.g., programming or erasing) on the rest of the array (orsome portion thereof, may compensate for the varying effects mentionedabove, such as but not limited to, ambient temperature, cell criticaldimensions, array architecture, and others. Moreover, this operationpulse may be analyzed, such as by a processor. The analysis of thisoperation pulse may be added to previous analysis and may determine theone operating pulse that singly changes electrical, physical and/ormechanical properties of the bits a predefined amount. The additionalanalysis of the operation pulses on the set of bits is referred to asthe continuous learning phase (steps 103–111). It is noted that thecontinuous learning phase may be used to achieve a better thresholddistribution control.

After applying the further operating pulse, the threshold voltage levelsof the bits may be verified (step 109) to determine if the thresholdvoltage levels have reached a predefined level (step 110). If thethreshold voltage levels have reached the predefined level forprogramming or erase, the operation method ends. If the thresholdvoltage levels of a certain amount of bits have not yet reached thepredefined level for programming or erase, then one or more operatingpulses of the same value, or alternatively a different value, based onthe continuous learning phase, may be applied to those bits orcollectively to the bits of the array (step 111). The procedure may thencontinue until all of the bits (or a predetermined number of bits) havepassed the verification step.

The additional operation pulse may be analyzed if it is done within apredefined period of time (step 112). The time criteria may be theambient conditions within the array, such as the temperature andvoltages, for example

Reference is now made to FIG. 4, which illustrates a simplified graphcomparing the distribution of the threshold voltages of the cells of theentire array after different applications of programming pulses, showingthe number of bits (2n) versus the threshold voltage in volts. Curve 83is the distribution of the threshold voltages of the cells of the entirearray after application of a single programming pulse. The distributionis relatively wide. Curve 84 is the distribution of the thresholdvoltages of the cells of the entire array after a plurality of steppedprogramming pulses. The distribution is relatively narrow. Curve 85 isthe distribution of the threshold voltages of the cells of the entirearray after a single programming pulse (determined during the learningphase, as described hereinabove) plus an additional supplementaryprogramming pulse, in accordance with an embodiment of the presentinvention. It is seen by comparing curves 84 and 85 that the finaldistributions of the threshold voltages are very similar. Thus, astepped programming algorithm for the entire array may be replaced by asingle programming pulse or a single pulse plus an additional pulse withvirtually the same results, thereby significantly improving programmingspeed.

It will be appreciated by persons skilled in the art that thedistribution of the threshold voltages of the cells of the entire arrayafter a single programming pulse (determined during the continuouslearning phase as described hereinabove) plus an additionalsupplementary programming pulse, in accordance with an embodiment of thepresent invention, may significantly further improve programming speed,because the operation pulse may be determined based on the analysis of amounting set of operated cells. Since the continuous learning phase maybe performed on a mounting set of operated cells, it may lead to afaster convergence to a desired programmed threshold voltage level.

It is noted that a method for operating bits of memory cells in a memorycell array, in accordance with an embodiment of the present invention,may begin with a preliminary step to determine the operation modewhether an array or a portion thereof will be operated with a learningphase, a continuous learning phase or without any of the above.

It is noted that the majority of the array cells may be fully programmedafter the first programming pulse. Only a small distribution may requireone higher programming pulse and a negligible amount of cells mayrequire even higher pulses. It may be possible to achieve one pulseprogramming and obtain high writing speeds, with the method of theinvention

Reference is now made to FIG. 5, which illustrates a simplified blockdiagram of a Control Circuit 200, a Memory Array 300, and a SenseAmplifier 400, in accordance with an embodiment of the presentinvention. Control Circuit 200 may operate a set of memory cells inMemory Array 300. The set size may be any arbitrary size, such as butnot limited to, 64 cells, for example. Control Circuit 200 may include aCharge Circuit 210 which may be adapted to produce a first operatingpulse to a terminal of a first cell in Memory Array 200, and intended toplace the first cell into a predefined state (i.e., programmed to atarget state, read or erased). A Logic Unit 220 may be included in theControl Circuit 200 as well. Logic Unit 220 may be adapted to determinepulse characteristics of a second operating pulse as a function of theresponse of the first cell to the first operating pulse. Logic Unit 220may be further adapted to determine pulse characteristics of a thirdoperating pulse as a function of the response of the first cell and thesecond cell in Memory Array 300 to the first and second operatingpulses, respectively Control Circuit 200 may include an internal MemoryBuffer 230 which may be adapted to store data received from SenseAmplifier 400, before it may be analyzed by Logic Unit 220. SenseAmplifier 400 may be adapted to determine the response of the bits tothe operation pulses.

It is noted that the pulse characteristics of the operating pulses maybe adjusted by adjusting the duration of the operation pulse or byadjusting the amplitude of the operating pulse. Logic Unit 220 may beadapted to adjust the pulse characteristics in both ways

It will be appreciated by persons skilled in the art that the presentinvention is not limited by what has been particularly shown anddescribed herein above. Rather the scope of the invention is defined bythe claims that follow:

1. A method of operating a set of memory cells in a memory array, themethod comprising: applying a first operating pulse to a terminal of afirst cell, wherein the first operating pulse is intended to place thefirst cell into a predefined state; and applying a second operatingpulse to a terminal of a second cell, wherein the second operating pulseis intended to place the second cell to the predefined state, andwherein the pulse characteristics of the second operating pulse are afunction of the response of the first cell to the first operating pulse.2. The method according to claim 1, further comprising a step ofapplying a third operating pulse to a terminal of a third cell, whereinthe third operating pulse is intended to place the third cell to saidpredefined state, and wherein the pulse characteristics of the thirdpulse are a function of the response of the first and the second cellsto the first and the second operating pulses, respectively.
 3. Themethod according to claim 1, wherein said pulse characteristics of thesecond operating pulse are adjusted by adjusting the duration of thesecond operation pulse.
 4. The method according to claim 1, wherein saidpulse characteristics of the second operation pulse are adjusted byadjusting the amplitude of said second operation pulse.